Many ICs are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. CMOS circuits and fabrication technology are commonly used in complex ICs. A necessary byproduct of the fabrication of a Bulk CMOS structure is a pair of parasitic bipolar junction transistors (“BJTs”). The collector of each BJT is connected to the base of the other transistor in a positive feedback structure. A phenomenon called latchup can occur when both BJT's conduct, creating a low resistance path between a voltage supply (e.g., VCC) and GND and the product of the gains of these two transistors in the feedback loop is greater than one. Latchup causes a high amount of current to flow through the device once it has been triggered, and causes a circuit malfunction, and in some cases, destroys the associated MOS device by electrical over stress.
Latchup can occur due to transients, a noise spike, bouncing due to switching, or improper hook-up of the I/O pad in a circuit application. Since latchup can cause an IC to fail, latchup immunity is often tested by driving a current into an I/O pad during device test. I/O pads are of particular concern because they are accessible to the user, which means they may be exposed to transients or other events during use that the IC manufacturer cannot control. Some I/O pads are connected to a pass gate, which can be an NMOS pass gate or a CMOS pass gate.
Techniques for avoiding latchup related to nmos pass gates connected to I/O pads are desirable.